LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Dff1 IS
   PORT(
       D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       ENABLE: IN STD_LOGIC;
       count :in std_logic_vector(2 DOWNTO 0);
       CLOCK :  IN STD_LOGIC;
	   Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END Dff1;

ARCHITECTURE structural OF Dff1 IS

BEGIN
PROCESS(D,CLOCK,ENABLE,count )
BEGIN
IF RISING_EDGE(CLOCK) and  ENABLE='1' and count/="000" and count/="001" THEN
Q<=D;
END IF;
END PROCESS;

END structural;


